Van der Waals engineering of ferroelectric heterostructures for long-retention memory

• Main Authors: Wang, Xiaowei, Zhu, Chao, Deng, Ya, Duan, Ruihuan, Chen, Jieqiong, Zeng, Qingsheng, Zhou, Jiadong, Fu, Qundong, You, Lu, Liu, Song, Edgar, James H., Yu, Peng, Liu, Zheng
• Other Authors: School of Materials Science and Engineering
• Format: Article
• Language: English
• Published: 2021
• Subjects: Engineering::Materials; Electronic Devices; Information Storage
• Online Access: https://hdl.handle.net/10356/146740
• Institution: Nanyang Technological University

The limited memory retention for a ferroelectric field-effect transistor has prevented the commercialization of its nonvolatile memory potential using the commercially available ferroelectrics. Here, we show a long-retention ferroelectric transistor memory cell featuring a metal-ferroelectric-metal-insulator-semiconductor architecture built from all van der Waals single crystals. Our device exhibits 17 mV dec−1 operation, a memory window larger than 3.8 V, and program/erase ratio greater than 107. Thanks to the trap-free interfaces and the minimized depolarization effects via van der Waals engineering, more than 104 cycles endurance, a 10-year memory retention and sub-5 μs program/erase speed are achieved. A single pulse as short as 100 ns is enough for polarization reversal, and a 4-bit/cell operation of a van der Waals ferroelectric transistor is demonstrated under a 100 ns pulse train. These device characteristics suggest that van der Waals engineering is a promising direction to improve ferroelectronic memory performance and reliability for future applications.