High performance fast feedthrough CMOS logic circuits

• Main Author: Qu, Yang.
• Other Authors: Lau, Kim Teen
• Format: Final Year Project
• Language: English
• Published: 2009
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
• Online Access: http://hdl.handle.net/10356/14746
• Institution: Nanyang Technological University

The Critical Voltage Transition Logic (CVTL) was proposed by in [1] [2]. The concept of the design is to maintain the output at as close to the VDD/2 as possible before confirming the actual output. It improves the speed by changing the rail to rail switching to nearly half of the rail to rail switching. Based on this concept, people proposed some improvements in its speed or power dissipation, such as “Low Power Critical Voltage Transition Logic” in [3]. Different designs based on critical voltage transition logic have been summarized in [4]. They named them as Fast Feedthrough logic families. The project explores and compares various configurations of Fast Feedthrough Logic (FTL) families. The operation principles of different configurations of FTL are investigated and analyzed. In order to compare their performance in term of speed, power dissipation and area with well known design technique such as complementary CMOS, Pseudo-NMOS Domino Logic and etc, different testing circuit have been employed which including inverter chain, XOR gate and XOR chain. Detailed performance comparisons have been done with varying transistor width, VDD and capacitive load. The problems and issues faced during certain condition (e.g. low VDD) will be highlighted and discussed. Because the feature of this design technique is suitable to arithmetic circuits. The project also verified the implementation on arithmetic circuits. Ripple Carry Adder (RCA) are used to test the implementation of FTL. The project also proposes some new designs based on the FTL. The new designs are mainly focus on the power dissipation issues. They are able to provide a relatively high speed with smaller tradeoff with power dissipation.