Lowering dynamic power of a stream-based CNN hardware accelerator

Lowering dynamic power of a stream-based CNN hardware accelerator

Custom hardware accelerators of Convolutional Neural Networks (CNN) provide a promising solution to meet real-time constraints for a wide range of applications on low-cost embedded devices. In this work, we aim to lower the dynamic power of a stream-based CNN hardware accelerator by reducing the com...

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Bibliographic Details
Main Authors: Piyasena, Duvindu, Wickramasinghe, Rukshan, Paul, Debdeep, Lam, Siew-Kei, Wu, Meiqing
Other Authors: School of Computer Science and Engineering
Format: Conference or Workshop Item
Language:English
Published: 2021
Subjects:
Engineering::Computer science and engineering::Hardware::Register-transfer-level implementation
Engineering::Computer science and engineering::Computing methodologies::Image processing and computer vision
FPGA
Convolutional Neural Networks
Online Access:https://hdl.handle.net/10356/147509
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Institution: Nanyang Technological University
Language: English
Description
Summary:Custom hardware accelerators of Convolutional Neural Networks (CNN) provide a promising solution to meet real-time constraints for a wide range of applications on low-cost embedded devices. In this work, we aim to lower the dynamic power of a stream-based CNN hardware accelerator by reducing the computational redundancies in the CNN layers. In particular, we investigate the redundancies due to the downsampling effect of max pooling layers which are prevalent in state-of-the-art CNNs, and propose an approximation method to reduce the overall computations. The experimental results show that the proposed method leads to lower dynamic power without sacrificing accuracy.

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