Lowering dynamic power of a stream-based CNN hardware accelerator

Custom hardware accelerators of Convolutional Neural Networks (CNN) provide a promising solution to meet real-time constraints for a wide range of applications on low-cost embedded devices. In this work, we aim to lower the dynamic power of a stream-based CNN hardware accelerator by reducing the com...

Full description

Saved in:
Bibliographic Details
Main Authors: Piyasena, Duvindu, Wickramasinghe, Rukshan, Paul, Debdeep, Lam, Siew-Kei, Wu, Meiqing
Other Authors: School of Computer Science and Engineering
Format: Conference or Workshop Item
Language:English
Published: 2021
Subjects:
Online Access:https://hdl.handle.net/10356/147509
Tags: Add Tag
No Tags, Be the first to tag this record!
Institution: Nanyang Technological University
Language: English
id sg-ntu-dr.10356-147509
record_format dspace
spelling sg-ntu-dr.10356-1475092021-04-19T03:27:20Z Lowering dynamic power of a stream-based CNN hardware accelerator Piyasena, Duvindu Wickramasinghe, Rukshan Paul, Debdeep Lam, Siew-Kei Wu, Meiqing School of Computer Science and Engineering 2019 IEEE 21st International Workshop on Multimedia Signal Processing (MMSP) Hardware & Embedded Systems Lab (HESL) Engineering::Computer science and engineering::Hardware::Register-transfer-level implementation Engineering::Computer science and engineering::Computing methodologies::Image processing and computer vision FPGA Convolutional Neural Networks Custom hardware accelerators of Convolutional Neural Networks (CNN) provide a promising solution to meet real-time constraints for a wide range of applications on low-cost embedded devices. In this work, we aim to lower the dynamic power of a stream-based CNN hardware accelerator by reducing the computational redundancies in the CNN layers. In particular, we investigate the redundancies due to the downsampling effect of max pooling layers which are prevalent in state-of-the-art CNNs, and propose an approximation method to reduce the overall computations. The experimental results show that the proposed method leads to lower dynamic power without sacrificing accuracy. National Research Foundation (NRF) Accepted version This research project is funded by the National Research Foundation Singapore under its Campus for Research Excellence and Technological Enterprise (CREATE) programme with the Technical University of Munich at TUMCREATE. 2021-04-19T03:27:20Z 2021-04-19T03:27:20Z 2019 Conference Paper Piyasena, D., Wickramasinghe, R., Paul, D., Lam, S. & Wu, M. (2019). Lowering dynamic power of a stream-based CNN hardware accelerator. 2019 IEEE 21st International Workshop on Multimedia Signal Processing (MMSP), 1-6. https://dx.doi.org/10.1109/MMSP.2019.8901777 9781728118178 https://hdl.handle.net/10356/147509 10.1109/MMSP.2019.8901777 2-s2.0-85075739729 1 6 en TUM CREATE © 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: https://doi.org/10.1109/MMSP.2019.8901777 application/pdf
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
language English
topic Engineering::Computer science and engineering::Hardware::Register-transfer-level implementation
Engineering::Computer science and engineering::Computing methodologies::Image processing and computer vision
FPGA
Convolutional Neural Networks
spellingShingle Engineering::Computer science and engineering::Hardware::Register-transfer-level implementation
Engineering::Computer science and engineering::Computing methodologies::Image processing and computer vision
FPGA
Convolutional Neural Networks
Piyasena, Duvindu
Wickramasinghe, Rukshan
Paul, Debdeep
Lam, Siew-Kei
Wu, Meiqing
Lowering dynamic power of a stream-based CNN hardware accelerator
description Custom hardware accelerators of Convolutional Neural Networks (CNN) provide a promising solution to meet real-time constraints for a wide range of applications on low-cost embedded devices. In this work, we aim to lower the dynamic power of a stream-based CNN hardware accelerator by reducing the computational redundancies in the CNN layers. In particular, we investigate the redundancies due to the downsampling effect of max pooling layers which are prevalent in state-of-the-art CNNs, and propose an approximation method to reduce the overall computations. The experimental results show that the proposed method leads to lower dynamic power without sacrificing accuracy.
author2 School of Computer Science and Engineering
author_facet School of Computer Science and Engineering
Piyasena, Duvindu
Wickramasinghe, Rukshan
Paul, Debdeep
Lam, Siew-Kei
Wu, Meiqing
format Conference or Workshop Item
author Piyasena, Duvindu
Wickramasinghe, Rukshan
Paul, Debdeep
Lam, Siew-Kei
Wu, Meiqing
author_sort Piyasena, Duvindu
title Lowering dynamic power of a stream-based CNN hardware accelerator
title_short Lowering dynamic power of a stream-based CNN hardware accelerator
title_full Lowering dynamic power of a stream-based CNN hardware accelerator
title_fullStr Lowering dynamic power of a stream-based CNN hardware accelerator
title_full_unstemmed Lowering dynamic power of a stream-based CNN hardware accelerator
title_sort lowering dynamic power of a stream-based cnn hardware accelerator
publishDate 2021
url https://hdl.handle.net/10356/147509
_version_ 1698713666286780416