Simulation of 1T1R (one-transistor one ReRAM) memory cell

The memristor is the fourth essential circuit element besides resistor, inductor, and capacitor. It is considered the next generation of non-volatile memory technology, with high speed, low power consumption, easy integration, compatibility with CMOS technology, and other advantages. It can satisfy...

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Bibliographic Details
Main Author: Chen, Bo
Other Authors: Chen Tupei
Format: Thesis-Master by Coursework
Language:English
Published: Nanyang Technological University 2021
Subjects:
Online Access:https://hdl.handle.net/10356/149416
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Institution: Nanyang Technological University
Language: English
Description
Summary:The memristor is the fourth essential circuit element besides resistor, inductor, and capacitor. It is considered the next generation of non-volatile memory technology, with high speed, low power consumption, easy integration, compatibility with CMOS technology, and other advantages. It can satisfy general-purpose electronic memory's performance requirements for next-generation high-density information storage and high-performance computing. Meanwhile, the memristor can realize non-volatile state logic operations and neuromorphic computing, integrate information storage, and calculate in a single device, which can be used as fundamental components in storage-computing fusion non-Turing model and non-Von Neumann computing architecture. Memristors have a milestone significance and a cornerstone role in major strategic areas such as ultra-high-density information storage, ultra-high-performance computing, and neuromorphic artificial intelligence in the era of big data. This dissertation focused on designing the 1T1R (one-transistor one ReRAM) memory cell circuit. The project consists of two parts: the first part is to build a SPICE model for ReRAM of which physical mechanism during the SET/RESET process can be manifested completely. The SPICE code for this ReRAM was mainly based on the ‘Verilog-A Compact Model for Oxide-based Resistive Random Access Memory’ developed by Jane Shimeng Yu, el ta. from Stanford University. The second part is to construct a 1T1R memory cell circuit with an n-channel MOSFET of TSMC 0.18um CMOS process and a ReRAM model built in the first part. The I-V characteristic and the transient response of the 1T1R cell have been simulated with LTspice. Furthermore, based on the analysis of the simulation results, methods are proposed to solve the numerical convergence problem occurring during the SPICE code running with the LTspice simulator.