A hierarchical multiclassifier system for automated analysis of delayered IC images

A hierarchical multiclassifier system for automated analysis of delayered IC images

A robust and accurate machine learning based hierarchical multiclassifier system is proposed to automate the retrieval of interconnection information from delayered integrated circuits images. The proposed system replaces labor-intensive manual annotation process and provides an effective approach f...

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Main Authors: Cheng, Deruo, Shi, Yiqiong, Gwee, Bah-Hwee, Toh, Kar-Ann, Lin, Tong
Other Authors: School of Electrical and Electronic Engineering
Format: Article
Language:English
Published: 2021
Subjects:
Engineering::Electrical and electronic engineering
Shape
Integrated Circuits
Online Access:https://hdl.handle.net/10356/150807
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Institution: Nanyang Technological University
Language: English
id sg-ntu-dr.10356-150807
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spelling sg-ntu-dr.10356-1508072021-06-09T01:31:08Z A hierarchical multiclassifier system for automated analysis of delayered IC images Cheng, Deruo Shi, Yiqiong Gwee, Bah-Hwee Toh, Kar-Ann Lin, Tong School of Electrical and Electronic Engineering Temasek Laboratories @ NTU Engineering::Electrical and electronic engineering Shape Integrated Circuits A robust and accurate machine learning based hierarchical multiclassifier system is proposed to automate the retrieval of interconnection information from delayered integrated circuits images. The proposed system replaces labor-intensive manual annotation process and provides an effective approach for the automated analysis of state-of-the-art deep submicron IC chips. 2021-06-09T01:31:08Z 2021-06-09T01:31:08Z 2019 Journal Article Cheng, D., Shi, Y., Gwee, B., Toh, K. & Lin, T. (2019). A hierarchical multiclassifier system for automated analysis of delayered IC images. IEEE Intelligent Systems, 34(2), 36-43. https://dx.doi.org/10.1109/MIS.2018.2886669 1541-1672 https://hdl.handle.net/10356/150807 10.1109/MIS.2018.2886669 2-s2.0-85058663657 2 34 36 43 en IEEE Intelligent Systems © 2018 IEEE. All rights reserved.
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
language English
topic Engineering::Electrical and electronic engineering
Shape
Integrated Circuits
spellingShingle Engineering::Electrical and electronic engineering
Shape
Integrated Circuits
Cheng, Deruo
Shi, Yiqiong
Gwee, Bah-Hwee
Toh, Kar-Ann
Lin, Tong
A hierarchical multiclassifier system for automated analysis of delayered IC images
description A robust and accurate machine learning based hierarchical multiclassifier system is proposed to automate the retrieval of interconnection information from delayered integrated circuits images. The proposed system replaces labor-intensive manual annotation process and provides an effective approach for the automated analysis of state-of-the-art deep submicron IC chips.
author2 School of Electrical and Electronic Engineering
author_facet School of Electrical and Electronic Engineering
Cheng, Deruo
Shi, Yiqiong
Gwee, Bah-Hwee
Toh, Kar-Ann
Lin, Tong
format Article
author Cheng, Deruo
Shi, Yiqiong
Gwee, Bah-Hwee
Toh, Kar-Ann
Lin, Tong
author_sort Cheng, Deruo
title A hierarchical multiclassifier system for automated analysis of delayered IC images
title_short A hierarchical multiclassifier system for automated analysis of delayered IC images
title_full A hierarchical multiclassifier system for automated analysis of delayered IC images
title_fullStr A hierarchical multiclassifier system for automated analysis of delayered IC images
title_full_unstemmed A hierarchical multiclassifier system for automated analysis of delayered IC images
title_sort hierarchical multiclassifier system for automated analysis of delayered ic images
publishDate 2021
url https://hdl.handle.net/10356/150807
_version_ 1702431178043162624

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