Reduced worst-case communication latency using single-cycle multi-hop traversal network-on-chip

The communication latency in traditional Network-on-Chip (NoC) with hop-by-hop traversal is inherently restricted by the distance between source-destination communicating pairs. SMART, as one of the dynamically reconfigurable NoC architectures, enables the new feature of single-cycle long-distance c...

Full description

Saved in:
Bibliographic Details
Main Authors: Chen, Peng, Liu, Weichen, Chen, Hui, Li, Shiqing, Li, Mengquan, Yang, Lei, Guan, Nan
Other Authors: School of Computer Science and Engineering
Format: Article
Language:English
Published: 2021
Subjects:
Online Access:https://hdl.handle.net/10356/151848
Tags: Add Tag
No Tags, Be the first to tag this record!
Institution: Nanyang Technological University
Language: English
id sg-ntu-dr.10356-151848
record_format dspace
spelling sg-ntu-dr.10356-1518482023-12-15T03:50:36Z Reduced worst-case communication latency using single-cycle multi-hop traversal network-on-chip Chen, Peng Liu, Weichen Chen, Hui Li, Shiqing Li, Mengquan Yang, Lei Guan, Nan School of Computer Science and Engineering Engineering::Computer science and engineering Real-time Systems Scheduling The communication latency in traditional Network-on-Chip (NoC) with hop-by-hop traversal is inherently restricted by the distance between source-destination communicating pairs. SMART, as one of the dynamically reconfigurable NoC architectures, enables the new feature of single-cycle long-distance communication by building a direct bypass path between distant cores dynamically at runtime. With the increasing of the number of integrated cores in multi/many-core systems, SMART has been deemed a promising communication backbone in such systems. However, SMART is generally optimized for average-case performance for best-effort traffics, not offering real-time guaranteed services for real-time traffics, and thus SMART often shows extremely poor real-time performance (e.g. schedulability). To make SMART latency-predictable for real-time traffics, by combining with the single-cycle bypass forwarding technique, in this paper, we firstly propose a priority-preemptive scheduling to allow contending packets to be arbitrated according to predefined priorities. Based on the priority-based scheduling, for the real-time packet flows with given flow mapping and predefined priorities, we then propose a real-time communication analysis model, by considering shared virtual channels (or priority levels) and arbitrary-deadline real-time packet flows, to predict the worst-case communication latency and validate the schedulability. Through theoretical and experimental comparison, the worst-case communication latency of the analyzed packet flows is reduced significantly compared with that of the traditional priority-preemptive NoCs with hop-by-hop traversal and the original distance-based SMART, thus improving the schedulability. Ministry of Education (MOE) Nanyang Technological University This work is partially supported by the National Natural Science Foundation of China (NSFC No. 61772094), the Ministry of Education, Singapore, under its Academic Research Fund Tier 2 (MOE2019-T2-1-071) and Tier 1 (MOE2019-T1-001-072), and Nanyang Technological University, Singapore, under its NAP (M4082282) and SUG (M4082087). 2021-07-05T06:25:41Z 2021-07-05T06:25:41Z 2021 Journal Article Chen, P., Liu, W., Chen, H., Li, S., Li, M., Yang, L. & Guan, N. (2021). Reduced worst-case communication latency using single-cycle multi-hop traversal network-on-chip. IEEE Transactions On Computer-Aided Design of Integrated Circuits and Systems, 40(7), 1381-1394. https://dx.doi.org/10.1109/TCAD.2020.3015440 0278-0070 https://hdl.handle.net/10356/151848 10.1109/TCAD.2020.3015440 7 40 1381 1394 en National Natural Science Foundation of China (NSFC No. 61772094) Ministry of Education, Singapore (MOE2019-T2-1-071, MOE2019-T1-001-072) Nanyang Technological University, Singapore (M4082282, M4082087) IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 10.21979/N9/WIQKUF © 2021 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: https://doi.org/10.1109/TCAD.2020.3015440 application/pdf
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
language English
topic Engineering::Computer science and engineering
Real-time Systems
Scheduling
spellingShingle Engineering::Computer science and engineering
Real-time Systems
Scheduling
Chen, Peng
Liu, Weichen
Chen, Hui
Li, Shiqing
Li, Mengquan
Yang, Lei
Guan, Nan
Reduced worst-case communication latency using single-cycle multi-hop traversal network-on-chip
description The communication latency in traditional Network-on-Chip (NoC) with hop-by-hop traversal is inherently restricted by the distance between source-destination communicating pairs. SMART, as one of the dynamically reconfigurable NoC architectures, enables the new feature of single-cycle long-distance communication by building a direct bypass path between distant cores dynamically at runtime. With the increasing of the number of integrated cores in multi/many-core systems, SMART has been deemed a promising communication backbone in such systems. However, SMART is generally optimized for average-case performance for best-effort traffics, not offering real-time guaranteed services for real-time traffics, and thus SMART often shows extremely poor real-time performance (e.g. schedulability). To make SMART latency-predictable for real-time traffics, by combining with the single-cycle bypass forwarding technique, in this paper, we firstly propose a priority-preemptive scheduling to allow contending packets to be arbitrated according to predefined priorities. Based on the priority-based scheduling, for the real-time packet flows with given flow mapping and predefined priorities, we then propose a real-time communication analysis model, by considering shared virtual channels (or priority levels) and arbitrary-deadline real-time packet flows, to predict the worst-case communication latency and validate the schedulability. Through theoretical and experimental comparison, the worst-case communication latency of the analyzed packet flows is reduced significantly compared with that of the traditional priority-preemptive NoCs with hop-by-hop traversal and the original distance-based SMART, thus improving the schedulability.
author2 School of Computer Science and Engineering
author_facet School of Computer Science and Engineering
Chen, Peng
Liu, Weichen
Chen, Hui
Li, Shiqing
Li, Mengquan
Yang, Lei
Guan, Nan
format Article
author Chen, Peng
Liu, Weichen
Chen, Hui
Li, Shiqing
Li, Mengquan
Yang, Lei
Guan, Nan
author_sort Chen, Peng
title Reduced worst-case communication latency using single-cycle multi-hop traversal network-on-chip
title_short Reduced worst-case communication latency using single-cycle multi-hop traversal network-on-chip
title_full Reduced worst-case communication latency using single-cycle multi-hop traversal network-on-chip
title_fullStr Reduced worst-case communication latency using single-cycle multi-hop traversal network-on-chip
title_full_unstemmed Reduced worst-case communication latency using single-cycle multi-hop traversal network-on-chip
title_sort reduced worst-case communication latency using single-cycle multi-hop traversal network-on-chip
publishDate 2021
url https://hdl.handle.net/10356/151848
_version_ 1787136678859636736