Reduced worst-case communication latency using single-cycle multi-hop traversal network-on-chip

Reduced worst-case communication latency using single-cycle multi-hop traversal network-on-chip

The communication latency in traditional Network-on-Chip (NoC) with hop-by-hop traversal is inherently restricted by the distance between source-destination communicating pairs. SMART, as one of the dynamically reconfigurable NoC architectures, enables the new feature of single-cycle long-distance c...

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書目詳細資料
Main Authors:	Chen, Peng, Liu, Weichen, Chen, Hui, Li, Shiqing, Li, Mengquan, Yang, Lei, Guan, Nan
其他作者:	School of Computer Science and Engineering
格式:	Article
語言:	English
出版:	2021
主題:	Engineering::Computer science and engineering Real-time Systems Scheduling
在線閱讀:	https://hdl.handle.net/10356/151848
標簽:	添加標簽沒有標簽, 成為第一個標記此記錄!

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