A 14-b, 850fs fully synthesizable stochastic-based branching time-to-digital converter in 65nm CMOS

• Main Authors: Teh, Jian Sen, Siek, Liter, Alonso, Abdel Martinez, Firdauzi, Anugerah, Matsuzawa, Akira
• Other Authors: School of Electrical and Electronic Engineering
• Format: Conference or Workshop Item
• Language: English
• Published: 2021
• Subjects: Engineering::Electrical and electronic engineering; Time-to-Digital Converter (TDC); Branching
• Online Access: https://hdl.handle.net/10356/152114
• Institution: Nanyang Technological University

As technology advances, digital circuits are reaping the benefits more than its analog counterpart. Time-to-Digital converters (TDC) are aiding the transition of some traditionally analog circuits into the digital domain. In this paper, a 14-bits fully synthesizable stochastic-based branching TDC is proposed. As compared to prior work, it has its own oscillation source on-chip. Moreover, it has a coarse-fine architecture with a smooth coarse-fine interface that allows it to extend its range easily without incurring large overhead costs. It was synthesized in a standard 65nm/1.2V CMOS technology using a VDD of 0.8 V. It is expected to achieve a resolution of 850fs. Simulation results shows a DNL & INL of 0.27 & 2.94LSB respectively, with a FoM of 136/J/conv. step. At a sampling rate of 125MS/s, it consumes 70.8mWof power.