A 12-bit branching time-to-digital converter with power saving features and digital based resolution tuning for PVT variations

• Main Authors: Teh, Jian Sen, Siek, Liter
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2021
• Subjects: Engineering::Electrical and electronic engineering; Time-to-Digital Converter; Bridging Capacitors; Branching
• Online Access: https://hdl.handle.net/10356/152448
• Institution: Nanyang Technological University

This paper presents a 12-bit branching Time-to-Digital converter (TDC) fabricated in a 40 nm CMOS technology. It composes of a 6-bit coarse counter TDC, and a 6-bit fine TDC. The fine TDC utilizes a proposed branching technique to interpolate between the phases of a 16-stage gated ring oscillator, increasing its number of phases from 16 to 64. Therefore, the TDC resolution is improved to be 4 times finer. The TDC incorporates fully digital based resolution tuning capability that enables its resolution to be more stable over PVT variations. Measurement results show that the resolution tuning reduces the resolution variation by 92.3% over a temperature range of − 40 to 125 °C. However, the simple resolution tuning method causes the TDC to have a relatively large resolution of 36.2 ps. The trade-offs between TDC resolution, yield, and scalability are discussed. The proposed TDC uses simple gated inverters based samplers instead of conventional arbiters to reduce power and area consumption. In addition, power gating features of the proposed TDC enable a low power consumption of 275 µW at a sampling rate of 5 MS/s. Without any linearity calibrations, the TDC DNL, INL, single-shot precision, and figure-of-merit are measured to be 1.30 LSB, 3.61 LSB, 0.75 LSB, and 61.9 fJ/conv.-step, respectively.