A 600-mA, fast-transient low-dropout regulator with pseudo-ESR technique in 0.18-μm CMOS process

• Main Authors: Li, K., Xiao, X., Jin, X., Zheng, Yuanjin
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2021
• Subjects: Engineering::Electrical and electronic engineering; Dual Loop Compensation (DLC); Loop Dtability
• Online Access: https://hdl.handle.net/10356/154483
• Institution: Nanyang Technological University

In this article, a dual loop-compensated, fast-transient, low-dropout regulator (LDO) is proposed for battery-powered applications. It is successfully implemented in a 0.18- μm CMOS process with a total silicon area of 210 μm × 593 μm. The proposed LDO is composed of two feedback loops. The fast feedback loop (FFL) employs direct output voltage spike detection through capacitive coupling, resulting in significantly improved, large signal transient response and loop bandwidth at the same time. Its voltage spike is 15 mV for a load step of 600 mA. The proposed LDO has a loop bandwidth of 2.3 MHz at a load current of 600 mA with a 30- μA no-load bias current. A power transistor with pseudo-equivalent series resistance (ESR) technique is proposed for loop stability improvement. It enables the usage of the low-cost, multilayer ceramic capacitors in mobile applications. The constant biased voltage feedback loop (VFL) has a loop gain larger than 60 dB under all load conditions, which enables a good line and load regulation.