A low-jitter and low-reference-spur 320 GHz signal source with an 80 GHz integer-N phase-locked loop using a quadrature XOR technique

• Main Authors: Liang, Yuan, Boon, Chirn Chye, Qi, Gengzhen, Dziallas, Giannino, Kissinger, Dietmar, Ng, Herman Jalli, Mak, Pui-In, Wang, Yong
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2022
• Subjects: Engineering::Electrical and electronic engineering::Integrated circuits; Frequency Detector; Harmonic Cancellation
• Online Access: https://hdl.handle.net/10356/156840
• Institution: Nanyang Technological University

This article reports a 320-GHz low-jitter and low-reference-spur signal source consisting of an 80-GHz integer-N phase-locked loop (PLL) and a 320-GHz frequency quadrupler. The 80-GHz PLL features a novel dual-path quadrature exclusive-OR (QXOR) technique to cancel the spurs at the reference frequency and its harmonics, enabling low-spur and low-noise phase locking. The proposed phase detector (PD) also enables frequency detection and lock detection (LD), rendering the band-searching to be decoupled from the loop components. Implemented in a 0.13-μm SiGe BiCMOS technology, the proposed signal source shows a -73.1-dBc reference spur, -113.7-dB/Hz phase noise at 1-MHz offset at 40.96 GHz, and -90.3-dB/Hz phase noise at 1-MHz offset at 311.8 GHz. It achieves an integrated jitter of 66.9 fs <formula> <tex>$_{{rms}}$</tex> </formula> at 40.96 GHz and 122 fs <formula> <tex>$_{{rms}}$</tex> </formula> (both integrated from 10 kHz to 100 MHz) beyond 300 GHz, with a total division ratio of 512. The LD time is at the microsecond level. The maximum output power is -3.24 dBm, and the power consumption is 372 mW.