A 40 GHz CMOS PLL with -75-dBc reference spur and 121.9-fs rms jitter featuring a quadrature sampling phase-frequency detector

• Main Authors: Liang, Yuan, Boon, Chirn Chye
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2022
• Subjects: Engineering::Electrical and electronic engineering::Integrated circuits; Integrated Jitter; CMOS Phase-Locked Loop
• Online Access: https://hdl.handle.net/10356/156845
• Institution: Nanyang Technological University

The high phase noise (PN) of CMOS millimeter-wave oscillators has encouraged the adoption of wide loop bandwidth for an integer-N phase-locked loop (PLL). This article proposes a quadrature sampling phase-frequency detector (QS-PFD) to disengage the tradeoff between spur rejection and loop bandwidth. With the introduction of an auxiliary path for phase detection, the spur generated by the main path is canceled without incurring extra power or degrading the loop stability. The high gain of the QS-PFD attenuates its jitter contribution to the loop. The QS-PFD enables fast frequency detection and lock detection. Implemented in 40-nm CMOS technology, the proposed PLL shows a -75-dBc reference spur, -101.5-dBc/Hz PN at a 1-MHz offset, and a minimum integrated jitter of 121.9 fs <formula> <tex>$_{{rms}}$</tex> </formula> (10 kHz-100 MHz) at 38.2 GHz with a division ratio of 128. The lock detection time is at the microsecond level. The proposed PLL consumes 23.6 mW from a 1.1-V power supply, leading to a figure of merit (FoM) of -245 dB.