Data transmission in clock domain crossing and data reconfiguration based on asynchronous FIFO
With the continuous development of electronic devices and VLSI manufacturing processes, the logic between high-speed processors has become increasingly complex, and more transistors have been integrated on the chip. And SoC has become the mainstream trend in chip manufacturing. Data transmission in...
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| Format: | Thesis-Master by Coursework |
| Language: | English |
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Nanyang Technological University
2022
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| Online Access: | https://hdl.handle.net/10356/161806 |
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| Institution: | Nanyang Technological University |
| Language: | English |
| Summary: | With the continuous development of electronic devices and VLSI manufacturing processes, the logic between high-speed processors has become increasingly complex, and more transistors have been integrated on the chip. And SoC has become the mainstream trend in chip manufacturing. Data transmission in clock domain crossing is common in SoC designing process, which also brings a lot of problems including metastability and data loss to designers. In this project, an asynchronous FIFO is designed to solve such problems. And then, an intellectual property core based on FIFO is designed to transfer a bulk of data in cross-clock domain and reconfigure the data. |
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