Clock data recovery circuits

This thesis presents the design and circuit implementation of a Clock Continuous Mode 2.5Gbps Data Recovery (CDR) circuit. The CDR is based on a new proposed dual-loop CDR architecture that doesn’t require the need of a lock detector. The operation is discussed in the report. The Foundary Design kit...

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Bibliographic Details
Main Author: Ong, Henry Kok Fong.
Other Authors: Ng Lian Soon
Format: Theses and Dissertations
Language:English
Published: 2011
Subjects:
Online Access:http://hdl.handle.net/10356/43528
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Institution: Nanyang Technological University
Language: English