Clock data recovery circuits
This thesis presents the design and circuit implementation of a Clock Continuous Mode 2.5Gbps Data Recovery (CDR) circuit. The CDR is based on a new proposed dual-loop CDR architecture that doesn’t require the need of a lock detector. The operation is discussed in the report. The Foundary Design kit...
Saved in:
Main Author: | Ong, Henry Kok Fong. |
---|---|
Other Authors: | Ng Lian Soon |
Format: | Theses and Dissertations |
Language: | English |
Published: |
2011
|
Subjects: | |
Online Access: | http://hdl.handle.net/10356/43528 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Institution: | Nanyang Technological University |
Language: | English |
Similar Items
-
Clock and data recovery circuits
by: Adaikkalam Raguraman
Published: (2010) -
CMOS building blocks for 10+Gb/s clock data recovery circuit
by: Liu, Haiqi
Published: (2010) -
Design of high-speed low-power clock and data recovery circuit
by: Alper, Cabuk
Published: (2008) -
Design of a hysteresis frequency lock detector for dual-loops clock and data recovery circuit
by: Tan, Yung Sern, et al.
Published: (2013) -
Design of a high speed and power efficient quarter-rate clock and data recovery circuit
by: Tan, Yung Sern
Published: (2012)