Design of a high speed and power efficient quarter-rate clock and data recovery circuit

• Main Author: Tan, Yung Sern
• Other Authors: Yeo Kiat Seng
• Format: Theses and Dissertations
• Language: English
• Published: 2012
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
• Online Access: https://hdl.handle.net/10356/50667
• Institution: Nanyang Technological University

Due to the advantage in technology and multi-media, the demand for data communication has increased tremendously. More standards for high speed low power communication have been established, i.e. Serial Advanced-Technology Attachment (SATA), Peripheral Component Interconnect Express (PCIe), Universa...