Design of a high speed and power efficient quarter-rate clock and data recovery circuit

• Main Author: Tan, Yung Sern
• Other Authors: Yeo Kiat Seng
• Format: Theses and Dissertations
• Language: English
• Published: 2012
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
• Online Access: https://hdl.handle.net/10356/50667
• Institution: Nanyang Technological University

Due to the advantage in technology and multi-media, the demand for data communication has increased tremendously. More standards for high speed low power communication have been established, i.e. Serial Advanced-Technology Attachment (SATA), Peripheral Component Interconnect Express (PCIe), Universal Serial Bus (USB) and etc. In the receiver design, the clock and data recovery (CDR) circuit is an important block as the clock signal is embedded in the receiving data. This thesis presents several new circuit designs to improve the performance of the CDR circuit. First, a new quarter-rate linear phase detector (PD) is proposed to reduce the circuit complexity of the reported quarter-rate linear PD design. Besides that, the proposed PD applies UP pulse-widening technique to resolve the issue of small UP pulses. The existing PDs with UP pulse-widening techniques have more output signals, which increases the difficulties in designing the Charge Pump (CP). In the proposed PD, the number of output signals has been successfully minimized. This thesis also provides propagation delay analysis of the proposed PD. A set of equations is derived from the analysis to predict the characteristic curve of the proposed PD. At the linear region, the accuracy of the prediction results is 98% of the simulation results. The effect on propagation delay at various phase differences is also being discussed.