Design of high-speed low-power clock and data recovery circuit

• المؤلف الرئيسي: Alper, Cabuk
• مؤلفون آخرون: Yeo, Kiat Seng
• التنسيق: Theses and Dissertations
• منشور في: 2008
• الموضوعات: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
• الوصول للمادة أونلاين: https://hdl.handle.net/10356/4801
• المؤسسة: Nanyang Technological University

In this thesis, the design of fully integrated high-speed low-power clock and data recovery (CDR) circuits in complementary metal-oxide-semiconductor (CMOS) devices for synchronous optical network (SONET) applications has been explored.