Design of high-speed low-power clock and data recovery circuit

• Main Author: Alper, Cabuk
• Other Authors: Yeo, Kiat Seng
• Format: Theses and Dissertations
• Published: 2008
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
• Online Access: https://hdl.handle.net/10356/4801
• Institution: Nanyang Technological University

In this thesis, the design of fully integrated high-speed low-power clock and data recovery (CDR) circuits in complementary metal-oxide-semiconductor (CMOS) devices for synchronous optical network (SONET) applications has been explored.