Design of high-speed low-power clock and data recovery circuit

• 主要作者: Alper, Cabuk
• 其他作者: Yeo, Kiat Seng
• 格式: Theses and Dissertations
• 出版: 2008
• 主題: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
• 在線閱讀: https://hdl.handle.net/10356/4801

In this thesis, the design of fully integrated high-speed low-power clock and data recovery (CDR) circuits in complementary metal-oxide-semiconductor (CMOS) devices for synchronous optical network (SONET) applications has been explored.