Design of high-speed low-power clock and data recovery circuit

In this thesis, the design of fully integrated high-speed low-power clock and data recovery (CDR) circuits in complementary metal-oxide-semiconductor (CMOS) devices for synchronous optical network (SONET) applications has been explored.

Saved in:

Bibliographic Details
Main Author:	Alper, Cabuk
Other Authors:	Yeo, Kiat Seng
Format:	Theses and Dissertations
Published:	2008
Subjects:	DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
Online Access:	https://hdl.handle.net/10356/4801
Tags:	Add Tag No Tags, Be the first to tag this record!
Institution:	Nanyang Technological University

id	sg-ntu-dr.10356-4801
record_format	dspace
spelling	sg-ntu-dr.10356-48012023-07-04T16:47:45Z Design of high-speed low-power clock and data recovery circuit Alper, Cabuk Yeo, Kiat Seng School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits In this thesis, the design of fully integrated high-speed low-power clock and data recovery (CDR) circuits in complementary metal-oxide-semiconductor (CMOS) devices for synchronous optical network (SONET) applications has been explored. DOCTOR OF PHILOSOPHY (EEE) 2008-09-17T09:59:01Z 2008-09-17T09:59:01Z 2006 2006 Thesis Alper, C. (2006). Design of high-speed low-power clock and data recovery circuit. Doctoral thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/4801 10.32657/10356/4801 Nanyang Technological University application/pdf
institution	Nanyang Technological University
building	NTU Library
continent	Asia
country	Singapore Singapore
content_provider	NTU Library
collection	DR-NTU
topic	DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
spellingShingle	DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits Alper, Cabuk Design of high-speed low-power clock and data recovery circuit
description	In this thesis, the design of fully integrated high-speed low-power clock and data recovery (CDR) circuits in complementary metal-oxide-semiconductor (CMOS) devices for synchronous optical network (SONET) applications has been explored.
author2	Yeo, Kiat Seng
author_facet	Yeo, Kiat Seng Alper, Cabuk
format	Theses and Dissertations
author	Alper, Cabuk
author_sort	Alper, Cabuk
title	Design of high-speed low-power clock and data recovery circuit
title_short	Design of high-speed low-power clock and data recovery circuit
title_full	Design of high-speed low-power clock and data recovery circuit
title_fullStr	Design of high-speed low-power clock and data recovery circuit
title_full_unstemmed	Design of high-speed low-power clock and data recovery circuit
title_sort	design of high-speed low-power clock and data recovery circuit
publishDate	2008
url	https://hdl.handle.net/10356/4801
_version_	1772826638258536448

Design of high-speed low-power clock and data recovery circuit

Similar Items