Design of a high speed and power efficient quarter-rate clock and data recovery circuit

• المؤلف الرئيسي: Tan, Yung Sern
• مؤلفون آخرون: Yeo Kiat Seng
• التنسيق: Theses and Dissertations
• اللغة: English
• منشور في: 2012
• الموضوعات: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
• الوصول للمادة أونلاين: https://hdl.handle.net/10356/50667

Due to the advantage in technology and multi-media, the demand for data communication has increased tremendously. More standards for high speed low power communication have been established, i.e. Serial Advanced-Technology Attachment (SATA), Peripheral Component Interconnect Express (PCIe), Universa...