Non-iterative division circuit design with accuracy and performance trade-off based on mixed integer linear programming approach

A wide range of applications such as image/video processing involve arithmetic division and demand high computing performance but can tolerate some degree of errors or allow small deviations from their theoretical results. This paper presents an approach for non-iterative arithmetic division circuit...

وصف كامل

محفوظ في:
التفاصيل البيبلوغرافية
المؤلفون الرئيسيون: Wu, Lei, Jong, Ching Chuen
مؤلفون آخرون: School of Electrical and Electronic Engineering
التنسيق: مقال
اللغة:English
منشور في: 2022
الموضوعات:
الوصول للمادة أونلاين:https://hdl.handle.net/10356/163281
الوسوم: إضافة وسم
لا توجد وسوم, كن أول من يضع وسما على هذه التسجيلة!
المؤسسة: Nanyang Technological University
اللغة: English
الوصف
الملخص:A wide range of applications such as image/video processing involve arithmetic division and demand high computing performance but can tolerate some degree of errors or allow small deviations from their theoretical results. This paper presents an approach for non-iterative arithmetic division circuit design, leveraging computation accuracy for high performance. The quotient is modeled as a curved surface and the surface is partitioned into many small rectangular planar stripes for linearity. Mixed integer linear programming is adopted to optimize the worst case error due to approximation in each stripe. As a result, an architecture for the division circuits consisting of simple additions and a small look-up table is achieved. The accuracy achieved in terms of the maximum absolute error percentage (MAEP) ranges from 0.44% to 0.11%. Comparing the proposed designs with the existing counterparts with similar MAEP, the area-delay product (ADP) is reduced by more than 40%. Compared to the counterpart with the closest ADP by the single stage logarithmic method, the proposed circuit has a smaller MAEP with 45% reduction. Comparing with the existing non-iterative division circuit by the curve fitting method, the proposed circuit has lowered MAEP and ADP by 21% and 27% respectively.