A scalable CMOS Ising computer featuring sparse and reconfigurable spin interconnects for solving combinatorial optimization problems
No existing algorithms can find exact solutions to the combinatorial optimization problems (COPs) classified as non-deterministic polynomial-time (NP) hard problems. Alternatively, Ising computer based on the Ising model and annealing process has recently drawn significant attention. The Ising compu...
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sg-ntu-dr.10356-1637452022-12-15T08:22:21Z A scalable CMOS Ising computer featuring sparse and reconfigurable spin interconnects for solving combinatorial optimization problems Su, Yuqi Mu, Junjie Kim, Hyunjoon Kim, Bongjin School of Electrical and Electronic Engineering Engineering::Electrical and electronic engineering Integrated Circuit Interconnections Computational Modeling No existing algorithms can find exact solutions to the combinatorial optimization problems (COPs) classified as non-deterministic polynomial-time (NP) hard problems. Alternatively, Ising computer based on the Ising model and annealing process has recently drawn significant attention. The Ising computers can find approximate solutions to the NP-hard COPs by observing the convergence of dynamic spin states. However, they have encountered challenges in mapping the optimization problems to the inflexible Ising computers with fixed spin interconnects. In this article, we propose a scalable CMOS Ising computer with sparse and reconfigurable spin interconnects for arbitrary mapping of spin networks with minimal overhead. Without a mapping algorithm, the proposed Ising computer provides a method for directly mapping COPs to the reconfigurable hardware. A 65-nm CMOS Ising test chip with 252 spins is fabricated and used for solving COPs, including max-cut problems. 2022-12-15T08:22:21Z 2022-12-15T08:22:21Z 2022 Journal Article Su, Y., Mu, J., Kim, H. & Kim, B. (2022). A scalable CMOS Ising computer featuring sparse and reconfigurable spin interconnects for solving combinatorial optimization problems. IEEE Journal of Solid-State Circuits, 57(3), 858-868. https://dx.doi.org/10.1109/JSSC.2022.3142896 0018-9200 https://hdl.handle.net/10356/163745 10.1109/JSSC.2022.3142896 2-s2.0-85123739676 3 57 858 868 en IEEE Journal of Solid-State Circuits © 2022 IEEE. All rights reserved. |
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Engineering::Electrical and electronic engineering Integrated Circuit Interconnections Computational Modeling Su, Yuqi Mu, Junjie Kim, Hyunjoon Kim, Bongjin A scalable CMOS Ising computer featuring sparse and reconfigurable spin interconnects for solving combinatorial optimization problems |
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No existing algorithms can find exact solutions to the combinatorial optimization problems (COPs) classified as non-deterministic polynomial-time (NP) hard problems. Alternatively, Ising computer based on the Ising model and annealing process has recently drawn significant attention. The Ising computers can find approximate solutions to the NP-hard COPs by observing the convergence of dynamic spin states. However, they have encountered challenges in mapping the optimization problems to the inflexible Ising computers with fixed spin interconnects. In this article, we propose a scalable CMOS Ising computer with sparse and reconfigurable spin interconnects for arbitrary mapping of spin networks with minimal overhead. Without a mapping algorithm, the proposed Ising computer provides a method for directly mapping COPs to the reconfigurable hardware. A 65-nm CMOS Ising test chip with 252 spins is fabricated and used for solving COPs, including max-cut problems. |
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School of Electrical and Electronic Engineering |
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School of Electrical and Electronic Engineering Su, Yuqi Mu, Junjie Kim, Hyunjoon Kim, Bongjin |
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Article |
author |
Su, Yuqi Mu, Junjie Kim, Hyunjoon Kim, Bongjin |
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Su, Yuqi |
title |
A scalable CMOS Ising computer featuring sparse and reconfigurable spin interconnects for solving combinatorial optimization problems |
title_short |
A scalable CMOS Ising computer featuring sparse and reconfigurable spin interconnects for solving combinatorial optimization problems |
title_full |
A scalable CMOS Ising computer featuring sparse and reconfigurable spin interconnects for solving combinatorial optimization problems |
title_fullStr |
A scalable CMOS Ising computer featuring sparse and reconfigurable spin interconnects for solving combinatorial optimization problems |
title_full_unstemmed |
A scalable CMOS Ising computer featuring sparse and reconfigurable spin interconnects for solving combinatorial optimization problems |
title_sort |
scalable cmos ising computer featuring sparse and reconfigurable spin interconnects for solving combinatorial optimization problems |
publishDate |
2022 |
url |
https://hdl.handle.net/10356/163745 |
_version_ |
1753801161683501056 |