Design of a CMOS voltage reference with output voltage doubling using modified 2-transistor topology

• Main Author: Li, Junyao
• Other Authors: Chan Pak Kwong
• Format: Thesis-Master by Coursework
• Language: English
• Published: Nanyang Technological University 2023
• Subjects: Engineering::Electrical and electronic engineering
• Online Access: https://hdl.handle.net/10356/164104
• Institution: Nanyang Technological University

This dissertation presents an ultra-low power CMOS voltage reference which operates in the subthreshold region. Modified from the conventional 2T circuit, the proposed circuit is capable to generate higher output voltage by using the resistor subdivision. The design comprises a negative-threshold native NMOS transistor as the current generator, a high-threshold PMOS transistor as the active load and an active voltage doubling network to generate the reference voltage. Implemented in TSMC 40nm CMOS technology, the proposed circuit operat es at a minimum supply of 0.65V and consumes 5.5nA. Under one sample simulation, the obtained T.C. is 16.64 ppm/°C and the nominal is 489.6mV (75.3% of ) of for the temperature range from -20°C to 80°C. For Monte-Carlo simulation of 200 samples at room temperature, the average output voltage is 488mV and the average T.C. is 29.6 ppm/°C whilst with the standard deviation of 13.26 ppm/°C. Finally, at room temperature, the proposed voltage reference has achieved a process sensitivity (σ/μ) of 3.9%, a line sensitivity of 0.51%/V and a power supply rejection of -45.5 dB and -76.3 dB at 1 Hz and 100 MHz. Compared to the representative prior-art works realized in same technology and similar supply current, the proposed circuit has offered the best 1-sampe T.C., the best average T.C. in multiple samples, the highest output voltage, the maximum output voltage per minimum supply voltage and the lowest process sensitivity in the output,