A 0.6 V 4 GS/s - 56.4 dB THD voltage-to-time converter in 28 nm CMOS

• Main Authors: Chen, Qian, Boon, Chirn Chye, Liang, Yuan
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2023
• Subjects: Engineering::Electrical and electronic engineering; Shrink Sampling; Time-Domain Signal Processing
• Online Access: https://hdl.handle.net/10356/165010
• Institution: Nanyang Technological University

A 0.6 V voltage-to-time converter (VTC) has been presented in this work for the emerging energy-efficient time-domain circuits and systems. The proposed VTC supports a rail-to-rail input by leveraging shrink sampling with two cascaded voltage sampling and charge sharing switches, breaking the tradeoff between linearity and input range of the traditional VTC and enabling low voltage operation. The charging current source is adjustable to calibrate the VTC gain variation. In addition, a 4-bit tunable delay buffer is inserted at the output stage to calibrate the VTC time offset, enhancing the PVT performance. By resizing the push-pull inverters' PMOS/NMOS size ratio in the output buffer chain, the jitter contribution from buffers has been reduced. It also recovers the signal's pulse width consumed during the voltage-time conversion, facilitating the time signal processing following VTC. Designed and fabricated in 28 nm CMOS, the prototype VTC occupies a 0.0012 mm2 active area. Measurement results show that the VTC can run up to 4 GHz at a 0.6 V power supply, achieving -56.4 dB total harmonic distortion (THD) with Nyquist input and consuming 2.1 mW.