Design of a >500MHz current starving VCO/DLL with low phase noise for digital PWM control

• Main Author: Chua, Dillon Yu Ze
• Other Authors: Siek Liter
• Format: Final Year Project
• Language: English
• Published: Nanyang Technological University 2023
• Subjects: Engineering::Electrical and electronic engineering
• Online Access: https://hdl.handle.net/10356/168475
• Institution: Nanyang Technological University

The fundamental building blocks of delay locked loops is the chain of delay elements that forms the delay lines. They are used in many VLSI circuits that require a clock distribution network. There are two popular methods implemented in a delay line. Namely, shunted capacitor delay elements and current starved element. The fundamental operation of a DLL is to compare an input signal with a reference signal and then delay the output to synchronize it with the reference signal. It typically consist of a voltage controlled delay line, a phase detector. A delay line consists of a chain of delay cells that can be varied to adjust the amount of delay between the output and input signal through the delay line. A voltage or current controlled delay line has a delay that is approximately proportional to the resistance-conductance time constant. When the resistance or conductance is adjusted, it will change the amount of delay in each delay cell. This is efficient in DLLs as precise, accurate and small amount of delay is achievable, giving well controlled variation in the delay. PLLs are normally used for high-frequency clock applications. However, when frequency multiplication is not needed, a DLL offers an advantage in performance over the PLL as it does not suffer on-chip noise and it has better stability. It is also less likely to accumulate jitter from power-supply and substrate noise. The quality of clock pulses is measured by frequency, phase, duty-cycle, jitter, and clock skew in general.