Design of a >500MHz current starving VCO/DLL with low phase noise for digital PWM control

The fundamental building blocks of delay locked loops is the chain of delay elements that forms the delay lines. They are used in many VLSI circuits that require a clock distribution network. There are two popular methods implemented in a delay line. Namely, shunted capacitor delay elements an...

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Bibliographic Details
Main Author: Chua, Dillon Yu Ze
Other Authors: Siek Liter
Format: Final Year Project
Language:English
Published: Nanyang Technological University 2023
Subjects:
Online Access:https://hdl.handle.net/10356/168475
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Institution: Nanyang Technological University
Language: English
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