Design of a >500MHz current starving VCO/DLL with low phase noise for digital PWM control

The fundamental building blocks of delay locked loops is the chain of delay elements that forms the delay lines. They are used in many VLSI circuits that require a clock distribution network. There are two popular methods implemented in a delay line. Namely, shunted capacitor delay elements an...

Full description

Saved in:
Bibliographic Details
Main Author: Chua, Dillon Yu Ze
Other Authors: Siek Liter
Format: Final Year Project
Language:English
Published: Nanyang Technological University 2023
Subjects:
Online Access:https://hdl.handle.net/10356/168475
Tags: Add Tag
No Tags, Be the first to tag this record!
Institution: Nanyang Technological University
Language: English
id sg-ntu-dr.10356-168475
record_format dspace
spelling sg-ntu-dr.10356-1684752023-07-07T15:46:12Z Design of a >500MHz current starving VCO/DLL with low phase noise for digital PWM control Chua, Dillon Yu Ze Siek Liter School of Electrical and Electronic Engineering ELSIEK@ntu.edu.sg Engineering::Electrical and electronic engineering The fundamental building blocks of delay locked loops is the chain of delay elements that forms the delay lines. They are used in many VLSI circuits that require a clock distribution network. There are two popular methods implemented in a delay line. Namely, shunted capacitor delay elements and current starved element. The fundamental operation of a DLL is to compare an input signal with a reference signal and then delay the output to synchronize it with the reference signal. It typically consist of a voltage controlled delay line, a phase detector. A delay line consists of a chain of delay cells that can be varied to adjust the amount of delay between the output and input signal through the delay line. A voltage or current controlled delay line has a delay that is approximately proportional to the resistance-conductance time constant. When the resistance or conductance is adjusted, it will change the amount of delay in each delay cell. This is efficient in DLLs as precise, accurate and small amount of delay is achievable, giving well controlled variation in the delay. PLLs are normally used for high-frequency clock applications. However, when frequency multiplication is not needed, a DLL offers an advantage in performance over the PLL as it does not suffer on-chip noise and it has better stability. It is also less likely to accumulate jitter from power-supply and substrate noise. The quality of clock pulses is measured by frequency, phase, duty-cycle, jitter, and clock skew in general. Bachelor of Engineering (Electrical and Electronic Engineering) 2023-06-13T06:42:01Z 2023-06-13T06:42:01Z 2023 Final Year Project (FYP) Chua, D. Y. Z. (2023). Design of a >500MHz current starving VCO/DLL with low phase noise for digital PWM control. Final Year Project (FYP), Nanyang Technological University, Singapore. https://hdl.handle.net/10356/168475 https://hdl.handle.net/10356/168475 en A2209-221 application/pdf Nanyang Technological University
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
language English
topic Engineering::Electrical and electronic engineering
spellingShingle Engineering::Electrical and electronic engineering
Chua, Dillon Yu Ze
Design of a >500MHz current starving VCO/DLL with low phase noise for digital PWM control
description The fundamental building blocks of delay locked loops is the chain of delay elements that forms the delay lines. They are used in many VLSI circuits that require a clock distribution network. There are two popular methods implemented in a delay line. Namely, shunted capacitor delay elements and current starved element. The fundamental operation of a DLL is to compare an input signal with a reference signal and then delay the output to synchronize it with the reference signal. It typically consist of a voltage controlled delay line, a phase detector. A delay line consists of a chain of delay cells that can be varied to adjust the amount of delay between the output and input signal through the delay line. A voltage or current controlled delay line has a delay that is approximately proportional to the resistance-conductance time constant. When the resistance or conductance is adjusted, it will change the amount of delay in each delay cell. This is efficient in DLLs as precise, accurate and small amount of delay is achievable, giving well controlled variation in the delay. PLLs are normally used for high-frequency clock applications. However, when frequency multiplication is not needed, a DLL offers an advantage in performance over the PLL as it does not suffer on-chip noise and it has better stability. It is also less likely to accumulate jitter from power-supply and substrate noise. The quality of clock pulses is measured by frequency, phase, duty-cycle, jitter, and clock skew in general.
author2 Siek Liter
author_facet Siek Liter
Chua, Dillon Yu Ze
format Final Year Project
author Chua, Dillon Yu Ze
author_sort Chua, Dillon Yu Ze
title Design of a >500MHz current starving VCO/DLL with low phase noise for digital PWM control
title_short Design of a >500MHz current starving VCO/DLL with low phase noise for digital PWM control
title_full Design of a >500MHz current starving VCO/DLL with low phase noise for digital PWM control
title_fullStr Design of a >500MHz current starving VCO/DLL with low phase noise for digital PWM control
title_full_unstemmed Design of a >500MHz current starving VCO/DLL with low phase noise for digital PWM control
title_sort design of a >500mhz current starving vco/dll with low phase noise for digital pwm control
publisher Nanyang Technological University
publishDate 2023
url https://hdl.handle.net/10356/168475
_version_ 1772828710320209920