Uniform etching for failure analysis of integrated circuits

Following the trend towards transistor miniaturization and power efficiency in Integrated Circuits (ICs), the concurrent miniaturization of possible defects challenges Failure Analysis (FA) engineers to accurately deprocess ICs with great precision before accessing the defects. As such, etch uniform...

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Main Author: Yeo, Aloysius Teng Howe
Other Authors: Gan Chee Lip
Format: Final Year Project
Language:English
Published: Nanyang Technological University 2023
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Online Access:https://hdl.handle.net/10356/169222
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Institution: Nanyang Technological University
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spelling sg-ntu-dr.10356-1692222023-07-15T16:45:27Z Uniform etching for failure analysis of integrated circuits Yeo, Aloysius Teng Howe Gan Chee Lip School of Materials Science and Engineering CLGan@ntu.edu.sg Engineering::Electrical and electronic engineering Engineering::Materials Following the trend towards transistor miniaturization and power efficiency in Integrated Circuits (ICs), the concurrent miniaturization of possible defects challenges Failure Analysis (FA) engineers to accurately deprocess ICs with great precision before accessing the defects. As such, etch uniformity is crucial to avoid accidental removal of defects. However, in the context of this research, thickness differences between the passivation layer, consisting of silicon nitride stacked above silicon dioxide, above and between metal lines inhibit the pursuit for uniform etch profiles. Hence, this research aims to develop a SF6/O2 etch recipe, using the Inductively Coupled Plasma Reactive Ion Etching (ICP RIE), with a high silicon nitride to silicon dioxide selectivity. By maximizing the etch selectivity, the objective is to overcome the thickness difference of the passivation layer (~400 nm) and minimize the extent of over etch as much as possible, whilst ensuring global uniformity. Upon formulation of the SF6/O2 recipe, an investigation regarding the presence of microloading effects as well as development of techniques to overcome edge effects was carried out to address possible sources of etch non-uniformities. Following that, three different etching techniques were being evaluated using the Field Emission Scanning Electron Microscope (FESEM) and Focused Ion Beam-Scanning Electron Microscope (FIB-SEM). By analysing the captured SEM images, the extent of over etch was measured and the technique involving a transition from low bias (silicon nitride removal) to high bias (silicon dioxide removal) yielded the best results due to an increase in etch selectivity from 3.5 to 8.7. The over etch was measured to be ~210 nm compared to a likely over etch of ~400 nm if an etch recipe with minimal selectivity was utilized. However, microtrenching effects have led to a pronounced etch rate at the corners of trenches, leading to those regions experiencing an over etch of ~340 nm. As such, future works may look into promoting more isotropic etch profiles to reduce the presence of slanted etch profiles which often results in microtrenching. Furthermore, despite improvements in the extent of over etch, ~210 nm is still not ideal for Physical FA (PFA) studies and future works may explore adding N2 gas into the recipe to further promote the nitride to oxide selectivity. Bachelor of Engineering (Materials Engineering) 2023-07-10T01:08:30Z 2023-07-10T01:08:30Z 2023 Final Year Project (FYP) Yeo, A. T. H. (2023). Uniform etching for failure analysis of integrated circuits. Final Year Project (FYP), Nanyang Technological University, Singapore. https://hdl.handle.net/10356/169222 https://hdl.handle.net/10356/169222 en application/pdf Nanyang Technological University
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
language English
topic Engineering::Electrical and electronic engineering
Engineering::Materials
spellingShingle Engineering::Electrical and electronic engineering
Engineering::Materials
Yeo, Aloysius Teng Howe
Uniform etching for failure analysis of integrated circuits
description Following the trend towards transistor miniaturization and power efficiency in Integrated Circuits (ICs), the concurrent miniaturization of possible defects challenges Failure Analysis (FA) engineers to accurately deprocess ICs with great precision before accessing the defects. As such, etch uniformity is crucial to avoid accidental removal of defects. However, in the context of this research, thickness differences between the passivation layer, consisting of silicon nitride stacked above silicon dioxide, above and between metal lines inhibit the pursuit for uniform etch profiles. Hence, this research aims to develop a SF6/O2 etch recipe, using the Inductively Coupled Plasma Reactive Ion Etching (ICP RIE), with a high silicon nitride to silicon dioxide selectivity. By maximizing the etch selectivity, the objective is to overcome the thickness difference of the passivation layer (~400 nm) and minimize the extent of over etch as much as possible, whilst ensuring global uniformity. Upon formulation of the SF6/O2 recipe, an investigation regarding the presence of microloading effects as well as development of techniques to overcome edge effects was carried out to address possible sources of etch non-uniformities. Following that, three different etching techniques were being evaluated using the Field Emission Scanning Electron Microscope (FESEM) and Focused Ion Beam-Scanning Electron Microscope (FIB-SEM). By analysing the captured SEM images, the extent of over etch was measured and the technique involving a transition from low bias (silicon nitride removal) to high bias (silicon dioxide removal) yielded the best results due to an increase in etch selectivity from 3.5 to 8.7. The over etch was measured to be ~210 nm compared to a likely over etch of ~400 nm if an etch recipe with minimal selectivity was utilized. However, microtrenching effects have led to a pronounced etch rate at the corners of trenches, leading to those regions experiencing an over etch of ~340 nm. As such, future works may look into promoting more isotropic etch profiles to reduce the presence of slanted etch profiles which often results in microtrenching. Furthermore, despite improvements in the extent of over etch, ~210 nm is still not ideal for Physical FA (PFA) studies and future works may explore adding N2 gas into the recipe to further promote the nitride to oxide selectivity.
author2 Gan Chee Lip
author_facet Gan Chee Lip
Yeo, Aloysius Teng Howe
format Final Year Project
author Yeo, Aloysius Teng Howe
author_sort Yeo, Aloysius Teng Howe
title Uniform etching for failure analysis of integrated circuits
title_short Uniform etching for failure analysis of integrated circuits
title_full Uniform etching for failure analysis of integrated circuits
title_fullStr Uniform etching for failure analysis of integrated circuits
title_full_unstemmed Uniform etching for failure analysis of integrated circuits
title_sort uniform etching for failure analysis of integrated circuits
publisher Nanyang Technological University
publishDate 2023
url https://hdl.handle.net/10356/169222
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