Design of CMOS bulk-drain driven operational amplifier for low-voltage analog signal-processing applications

• Main Author: Gao, Feifan
• Other Authors: Chan Pak Kwong
• Format: Thesis-Master by Coursework
• Language: English
• Published: Nanyang Technological University 2024
• Subjects: Engineering::Electrical and electronic engineering
• Online Access: https://hdl.handle.net/10356/172923
• Institution: Nanyang Technological University

This dissertation proposes a low-voltage CMOS four-stage amplifier operating in the subthreshold region. The first design technique includes the cross-feedforward positive feedback frequency compensation (CFPFC) for obtaining better bandwidth efficiency in low-voltage multi-stage amplifier. The second design technique incorporates both the bulk-drain driven input stage topology in conjunction with low-voltage attenuator to permit the operation of low-voltage amplifier and improves the input common-mode range (ICMR). The proposed circuit is implemented using TSMC-40 nm process technology. It consumes 0.866 μW at a supply voltage of 0.5 V. With a capacitive load of 50 pF, the four-stage amplifier can achieve 84.59 dB in gain, 161 kHz in unity-gain bandwidth, 96 degree in phase margin and 5.7 dB in gain margin whilst offering an input noise of 213.63 nV/√Hz @1kHz, small-signal power-bandwidth FoMss of 9.31 (MHz∙pF/μW), and noise-power per bandwidth based FoMnpb of 1.15×10-6 ((µV/√Hz)·µW/Hz). Compared to the conventional bulk-driven input stage design technique, it offers improved multi-parameter performance metric in terms of noise, power and bandwidth but at a compromising tradeoff on ICMR with respect to bulk-driven amplifier design. Compared with conventional gate-source input stage design, it offers improved ICMR. The amplifier is useful for low-voltage analog signal-processing applications.Besides, Flipped Gain Buffer (FGB) which offers rail-to-rail operation range, is also proposed to drive resistive load under ultra-low voltage, low-power applications. With the embedded buffer, the op-amp can drive a load of 300kΩ//50pF. For the op-amp without embedded buffer, the four-stage amplifier can achieve 79.7 dB in gain, 50 kHz in unity-gain bandwidth, 90 degree in phase margin and 19.5 dB in gain margin whilst exhibiting an input noise of 211 nV/√Hz @1kHz, and consuming 1.5 μW at a capacitive load of 50pF.