Exploration and design of SAR/SS ADC for in-memory computation
Compute-in-memory (CIM), as a solution to the von Neumann bottleneck, has gained widespread attention in recent years. In CIM operations, ADCs are typically required to convert analog voltages into digital codes. However, current CIM ADCs often demand substantial silicon area and operational power c...
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| Format: | Thesis-Master by Coursework |
| Language: | English |
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Nanyang Technological University
2024
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| Online Access: | https://hdl.handle.net/10356/173431 |
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| Institution: | Nanyang Technological University |
| Language: | English |
| Summary: | Compute-in-memory (CIM), as a solution to the von Neumann bottleneck, has gained widespread attention in recent years. In CIM operations, ADCs are typically required to convert analog voltages into digital codes. However, current CIM ADCs often demand substantial silicon area and operational power consumption. Therefore, the ADCs employed in CIM structures often impose high requirements on power consumption and silicon area. This paper presents the realization of a SAR/SS ADC with area efficiency. Starting from theoretical foundations, the overall design process is systematically discussed, with simulations conducted for each module. Specifically, an improved control logic based on the Sanyal switch is proposed for the ADC in this study. Simulations performed using 65nm technology demonstrate an ENOB of 10.31 bits, SNDR of 59.81 dB, SFDR of 72.05 dB, and a power consumption of 31.71 μW. The Figure of Merit (FOM) under the
supply voltage is calculated at 201 fJ/Conv.-step, with a sampling rate of 1/13 MS/s. This highlights the area efficiency of the proposed ADC.
Keywords: Compute-in-memory, SAR/SS ADC, area efficiency, improved control logic |
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