A high-accuracy and energy-efficient spiking neural network with On-FPGA STDP learning based on asynchronous CORDIC

• Main Author: Sheng, Shirui
• Other Authors: Lin Zhiping
• Format: Thesis-Master by Coursework
• Language: English
• Published: Nanyang Technological University 2024
• Subjects: Engineering
• Online Access: https://hdl.handle.net/10356/173705
• Institution: Nanyang Technological University

During the last few decades, Moore's law has propelled the anticipation of exponential growth in computing capabilities, primarily associated with silicon-based processing devices. However, as we approach the culmination of this trend, there is a compelling motivation to explore avenues toward embedded cognition. This exploration extends beyond merely augmenting computing power and encompasses a broader scope, including the reevaluation of computational organization and information representation. The pursuit of a paradigm shift in neuromorphic engineering is grounded in a dual objective: gaining deeper insights into the functioning of the human brain and fostering the development of more streamlined silicon processing devices. In emerging Spiking Neural Network (SNN) based hardware designs for neuromorphic systems, energy conservation and real-time learning stand out as appealing benefits. This dissertation introduces an efficient hardware design for biological neuron models, specifically the Leaky Integrate and Fire (LIF) neuron, using the COordinate Rotation DIgital Computer (CORDIC) algorithm. The asynchronous CORDIC (async-CORDIC) based design significantly improves accuracy and energy efficiency, outperforming conventional CORDIC approaches. We integrate CORDIC iterative pipelines with dual-rail logic using handshaking control, reducing switching activity and power dissipation by approximately 23%. Async-CORDIC design improves hardware efficiency, Spike-Timing Dependent Plasticity (STDP) based learning, and energy efficiency on FPGA, enhancing switching cycle utilization by 21% through fewer iteration stages. Our design reduces the average error in STDP exponentiation calculations by 5.4%. In real-world tasks, such as digit classification using the MNIST dataset, our implementation achieves up to approximately 95% accuracy.