Design of a 800-MHZ PLL in 28NM CMOS technology

• Main Author: Tao, Weiran
• Other Authors: Goh Wang Ling
• Format: Thesis-Master by Coursework
• Language: English
• Published: Nanyang Technological University 2024
• Subjects: Engineering; 28nm CMOS; Type–two charge pump PLL; Type–four PFD; Cascaded differential LC–VCO; Adjustable digital divider; Rail–to–rail output voltage; Low mismatch, spur and noise
• Online Access: https://hdl.handle.net/10356/175977
• Institution: Nanyang Technological University

This dissertation proposes a type–two analog PLL based on charge pump with division ratio of 20 and output frequency of up to 0.8GHz, which has been validated in 28nm CMOS technology system. The input signal is passed through a classic type–four phase and frequency detector, and then the current change is converted into a voltage signal through a charge pump. The third–order loop filter is applied to reduce high–frequency noise, its output voltage controls the cascaded differential LC voltage–controlled oscillator, which generates oscillation signals that are returned to the input of the phase and frequency detector through an adjustable digital divider, forming a feedback loop. This dissertation proposes, improves, and validates a novel charge pump structure that provides a wide range of rail–to–rail output voltage while significantly reducing mismatch. The power consumption of the entire PLL system measured at a power supply voltage of 1.8V is approximately 90mW, and the noise power is less than approximately -344dBc.