Design of a 800-MHZ PLL in 28NM CMOS technology
This dissertation proposes a type–two analog PLL based on charge pump with division ratio of 20 and output frequency of up to 0.8GHz, which has been validated in 28nm CMOS technology system. The input signal is passed through a classic type–four phase and frequency detector, and then the current cha...
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Nanyang Technological University
2024
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sg-ntu-dr.10356-1759772024-05-17T15:48:51Z Design of a 800-MHZ PLL in 28NM CMOS technology Tao, Weiran Goh Wang Ling School of Electrical and Electronic Engineering ewlgoh@ntu.edu.sg Engineering 28nm CMOS Type–two charge pump PLL Type–four PFD Cascaded differential LC–VCO Adjustable digital divider Rail–to–rail output voltage Low mismatch, spur and noise This dissertation proposes a type–two analog PLL based on charge pump with division ratio of 20 and output frequency of up to 0.8GHz, which has been validated in 28nm CMOS technology system. The input signal is passed through a classic type–four phase and frequency detector, and then the current change is converted into a voltage signal through a charge pump. The third–order loop filter is applied to reduce high–frequency noise, its output voltage controls the cascaded differential LC voltage–controlled oscillator, which generates oscillation signals that are returned to the input of the phase and frequency detector through an adjustable digital divider, forming a feedback loop. This dissertation proposes, improves, and validates a novel charge pump structure that provides a wide range of rail–to–rail output voltage while significantly reducing mismatch. The power consumption of the entire PLL system measured at a power supply voltage of 1.8V is approximately 90mW, and the noise power is less than approximately -344dBc. Master's degree 2024-05-13T01:45:21Z 2024-05-13T01:45:21Z 2024 Thesis-Master by Coursework Tao, W. (2024). Design of a 800-MHZ PLL in 28NM CMOS technology. Master's thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/175977 https://hdl.handle.net/10356/175977 en application/pdf Nanyang Technological University |
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Engineering 28nm CMOS Type–two charge pump PLL Type–four PFD Cascaded differential LC–VCO Adjustable digital divider Rail–to–rail output voltage Low mismatch, spur and noise |
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Engineering 28nm CMOS Type–two charge pump PLL Type–four PFD Cascaded differential LC–VCO Adjustable digital divider Rail–to–rail output voltage Low mismatch, spur and noise Tao, Weiran Design of a 800-MHZ PLL in 28NM CMOS technology |
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This dissertation proposes a type–two analog PLL based on charge pump with division ratio of 20 and output frequency of up to 0.8GHz, which has been validated in 28nm CMOS technology system. The input signal is passed through a classic type–four phase and frequency detector, and then the current change is converted into a voltage signal through a charge pump. The third–order loop filter is applied to reduce high–frequency noise, its output voltage controls the cascaded differential LC voltage–controlled oscillator, which generates oscillation signals that are returned to the input of the phase and frequency detector through an adjustable digital divider, forming a feedback loop. This dissertation proposes, improves, and validates a novel charge pump structure that provides a wide range of rail–to–rail output voltage while significantly reducing mismatch. The power consumption of the entire PLL system measured at a power supply voltage of 1.8V is approximately 90mW, and the noise power is less than approximately -344dBc. |
| author2 |
Goh Wang Ling |
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Goh Wang Ling Tao, Weiran |
| format |
Thesis-Master by Coursework |
| author |
Tao, Weiran |
| author_sort |
Tao, Weiran |
| title |
Design of a 800-MHZ PLL in 28NM CMOS technology |
| title_short |
Design of a 800-MHZ PLL in 28NM CMOS technology |
| title_full |
Design of a 800-MHZ PLL in 28NM CMOS technology |
| title_fullStr |
Design of a 800-MHZ PLL in 28NM CMOS technology |
| title_full_unstemmed |
Design of a 800-MHZ PLL in 28NM CMOS technology |
| title_sort |
design of a 800-mhz pll in 28nm cmos technology |
| publisher |
Nanyang Technological University |
| publishDate |
2024 |
| url |
https://hdl.handle.net/10356/175977 |
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1800916247382065152 |