Enhancing 3D NAND performance and reliability through overlay control
As microelectronic devices undergo continuous evolution, the ongoing miniaturization of semiconductor chips, coupled with an escalating number of layers, presents a huge challenge in meeting the progressively stringent overlay requirements for every successive generation of chips. Overlay, a metr...
Saved in:
Main Author: | Lim, Yu Le |
---|---|
Other Authors: | Lydia Helena Wong |
Format: | Final Year Project |
Language: | English |
Published: |
Nanyang Technological University
2024
|
Subjects: | |
Online Access: | https://hdl.handle.net/10356/175986 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Institution: | Nanyang Technological University |
Language: | English |
Similar Items
-
A cost-effective optimized design of a 3D NAND staircase integration flow
by: Zhang, Jinzhi
Published: (2023) -
Coding and signal processing for NAND flash memory
by: Chaudhry, Adnan Aslam
Published: (2017) -
Extending the lifetime of NAND flash memory by salvaging bad blocks
by: Wang, C., et al.
Published: (2013) -
TreeFTL: Efficient RAM management for high performance of NAND flash-based storage systems
by: Wang, C., et al.
Published: (2014) -
SAW: System-assisted wear leveling on the write endurance of NAND flash devices
by: Wang, C., et al.
Published: (2014)