Design and simulation of CMOS-based ternary logic arithmetic circuits using TSMC 40nm technology

• Main Author: Vivekanantham, Rithikha
• Other Authors: Tay Beng Kang
• Format: Final Year Project
• Language: English
• Published: Nanyang Technological University 2024
• Subjects: Engineering
• Online Access: https://hdl.handle.net/10356/176639
• Institution: Nanyang Technological University

In recent years, there has been growing interest in multi-valued logic (MVL) circuits, especially ternary logic circuits, due to their higher information density compared to binary logic systems. However, challenges persist regarding the fundamental construction of MVL circuit standard cells and the...