Design and simulation of CMOS-based ternary logic arithmetic circuits using TSMC 40nm technology
In recent years, there has been growing interest in multi-valued logic (MVL) circuits, especially ternary logic circuits, due to their higher information density compared to binary logic systems. However, challenges persist regarding the fundamental construction of MVL circuit standard cells and the...
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| 格式: | Final Year Project |
| 語言: | English |
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Nanyang Technological University
2024
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| 主題: | |
| 在線閱讀: | https://hdl.handle.net/10356/176639 |
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