Design of a differential 8-bit asynchronous SAR ADC for in-memory-computing
In-memory-computing is a possible alternative for conventional von Neumann architecture for its energy-efficient feature. ADC is a necessary peripheral block to convert the MAC result from the memory array to the digital signal. Among many types of ADCs, SAR ADC IS widely used in in-memory-computing...
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| Format: | Final Year Project |
| Language: | English |
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Nanyang Technological University
2024
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| Online Access: | https://hdl.handle.net/10356/176813 |
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| Institution: | Nanyang Technological University |
| Language: | English |
| Summary: | In-memory-computing is a possible alternative for conventional von Neumann architecture for its energy-efficient feature. ADC is a necessary peripheral block to convert the MAC result from the memory array to the digital signal. Among many types of ADCs, SAR ADC IS widely used in in-memory-computing circuits due to its efficient power behavior for low-resolution, low-power, medium-speed application, and the relatively simple realization. In this FYP, a differential 8-bit asynchronous SAR ADC for in-memory computing circuit is designed and tested. This report will introduce the track & hold (T&H), comparator, the capacitive digital-to-analog converter (CDAC) which uses custom MOM capacitor, the SAR logic and the asynchronous clock generator as components of designed SAR ADC. For the pre-layout simulation, the ENOB is tested as 7.73 bits under TT corner with input range 2.2V. The DNL is -0.118/+1.134LSB and INL is -0.123/+0.123LSB and the FOM is 19.66fJ. In the post-layout simulation, the ENOB under TT corner is 7.87 bits with input range 1.84V. |
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