Low power logic-in-memory circuit design

Low power logic-in-memory circuit design

This paper presents an analysis of power dissipation between conventional 6T SRAM memory arrays and SRAM memory arrays employing power reduction techniques. This study aims to assess the power efficiency of these power reduction techniques, which is crucial for low power applications in modern elect...

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Bibliographic Details
Main Author: Loe, Matthew Kit Wai
Other Authors: Kim Tae Hyoung
Format: Final Year Project
Language:English
Published: Nanyang Technological University 2024
Subjects:
Engineering
Online Access:https://hdl.handle.net/10356/176851
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Institution: Nanyang Technological University
Language: English
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spelling sg-ntu-dr.10356-1768512024-05-24T15:43:38Z Low power logic-in-memory circuit design Loe, Matthew Kit Wai Kim Tae Hyoung School of Electrical and Electronic Engineering THKIM@ntu.edu.sg Engineering This paper presents an analysis of power dissipation between conventional 6T SRAM memory arrays and SRAM memory arrays employing power reduction techniques. This study aims to assess the power efficiency of these power reduction techniques, which is crucial for low power applications in modern electronic devices. The 6T SRAM memory array made up of conventional 6T SRAM memory cells would be used as a baseline for comparison against other power optimized memory arrays. In conjunction with the power efficiency, varying supply voltage and temperature will be utilized to provide a more comprehensive set of data. The results show that these power reduction techniques is effective in better optimizing power. The research will involve tools such as Cadence Virtuoso and TSMC 65nm CMOS process technology. Bachelor's degree 2024-05-21T08:02:36Z 2024-05-21T08:02:36Z 2024 Final Year Project (FYP) Loe, M. K. W. (2024). Low power logic-in-memory circuit design. Final Year Project (FYP), Nanyang Technological University, Singapore. https://hdl.handle.net/10356/176851 https://hdl.handle.net/10356/176851 en application/pdf Nanyang Technological University
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
language English
topic Engineering
spellingShingle Engineering
Loe, Matthew Kit Wai
Low power logic-in-memory circuit design
description This paper presents an analysis of power dissipation between conventional 6T SRAM memory arrays and SRAM memory arrays employing power reduction techniques. This study aims to assess the power efficiency of these power reduction techniques, which is crucial for low power applications in modern electronic devices. The 6T SRAM memory array made up of conventional 6T SRAM memory cells would be used as a baseline for comparison against other power optimized memory arrays. In conjunction with the power efficiency, varying supply voltage and temperature will be utilized to provide a more comprehensive set of data. The results show that these power reduction techniques is effective in better optimizing power. The research will involve tools such as Cadence Virtuoso and TSMC 65nm CMOS process technology.
author2 Kim Tae Hyoung
author_facet Kim Tae Hyoung
Loe, Matthew Kit Wai
format Final Year Project
author Loe, Matthew Kit Wai
author_sort Loe, Matthew Kit Wai
title Low power logic-in-memory circuit design
title_short Low power logic-in-memory circuit design
title_full Low power logic-in-memory circuit design
title_fullStr Low power logic-in-memory circuit design
title_full_unstemmed Low power logic-in-memory circuit design
title_sort low power logic-in-memory circuit design
publisher Nanyang Technological University
publishDate 2024
url https://hdl.handle.net/10356/176851
_version_ 1800916192550977536

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