The design of a 10-bit segmented current steering digital-to-analog converter (SCSDAC)

The design of a 10-bit segmented current steering digital-to-analog converter (SCSDAC)

This thesis explores the design of a 10-bit Segmented Current Steering Digital-to-Analog Converter (SCSDAC), focusing on optimizing performance under stringent power constraints. The DAC is meticulously crafted to minimize power usage and maximize efficiency, aiming to operate below the conventional...

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Bibliographic Details
Main Author: Xu, Pengbo
Other Authors: Siek Liter
Format: Final Year Project
Language:English
Published: Nanyang Technological University 2024
Subjects:
Engineering
DAC
Low power
Online Access:https://hdl.handle.net/10356/177198
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Institution: Nanyang Technological University
Language: English
id sg-ntu-dr.10356-177198
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spelling sg-ntu-dr.10356-1771982024-05-31T15:43:50Z The design of a 10-bit segmented current steering digital-to-analog converter (SCSDAC) Xu, Pengbo Siek Liter School of Electrical and Electronic Engineering ELSIEK@ntu.edu.sg Engineering DAC Low power This thesis explores the design of a 10-bit Segmented Current Steering Digital-to-Analog Converter (SCSDAC), focusing on optimizing performance under stringent power constraints. The DAC is meticulously crafted to minimize power usage and maximize efficiency, aiming to operate below the conventional power usage of 10 to 50 milliwatts, with a targeted consumption under 20 microwatts. By refining the DAC architecture to address inherent limitations such as glitches and linearity, the study achieves a significant reduction in power consumption without compromising on the quality and efficiency of data conversion, which is critical for modern communication technologies. Bachelor's degree 2024-05-27T02:42:00Z 2024-05-27T02:42:00Z 2024 Final Year Project (FYP) Xu, P. (2024). The design of a 10-bit segmented current steering digital-to-analog converter (SCSDAC). Final Year Project (FYP), Nanyang Technological University, Singapore. https://hdl.handle.net/10356/177198 https://hdl.handle.net/10356/177198 en application/pdf Nanyang Technological University
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
language English
topic Engineering
DAC
Low power
spellingShingle Engineering
DAC
Low power
Xu, Pengbo
The design of a 10-bit segmented current steering digital-to-analog converter (SCSDAC)
description This thesis explores the design of a 10-bit Segmented Current Steering Digital-to-Analog Converter (SCSDAC), focusing on optimizing performance under stringent power constraints. The DAC is meticulously crafted to minimize power usage and maximize efficiency, aiming to operate below the conventional power usage of 10 to 50 milliwatts, with a targeted consumption under 20 microwatts. By refining the DAC architecture to address inherent limitations such as glitches and linearity, the study achieves a significant reduction in power consumption without compromising on the quality and efficiency of data conversion, which is critical for modern communication technologies.
author2 Siek Liter
author_facet Siek Liter
Xu, Pengbo
format Final Year Project
author Xu, Pengbo
author_sort Xu, Pengbo
title The design of a 10-bit segmented current steering digital-to-analog converter (SCSDAC)
title_short The design of a 10-bit segmented current steering digital-to-analog converter (SCSDAC)
title_full The design of a 10-bit segmented current steering digital-to-analog converter (SCSDAC)
title_fullStr The design of a 10-bit segmented current steering digital-to-analog converter (SCSDAC)
title_full_unstemmed The design of a 10-bit segmented current steering digital-to-analog converter (SCSDAC)
title_sort design of a 10-bit segmented current steering digital-to-analog converter (scsdac)
publisher Nanyang Technological University
publishDate 2024
url https://hdl.handle.net/10356/177198
_version_ 1800916367438774272

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