The design of a 10-bit segmented current steering digital-to-analog converter (SCSDAC)
This thesis explores the design of a 10-bit Segmented Current Steering Digital-to-Analog Converter (SCSDAC), focusing on optimizing performance under stringent power constraints. The DAC is meticulously crafted to minimize power usage and maximize efficiency, aiming to operate below the conventional...
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| 格式: | Final Year Project |
| 語言: | English |
| 出版: |
Nanyang Technological University
2024
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| 主題: | |
| 在線閱讀: | https://hdl.handle.net/10356/177198 |
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| 機構: | Nanyang Technological University |
| 語言: | English |