A radiation-hardened-by-design RISC-V microcontroller

• Main Author: Fang, Rouli
• Other Authors: Chang Joseph
• Format: Final Year Project
• Language: English
• Published: Nanyang Technological University 2024
• Subjects: Engineering; Microcontroller; RSIC-V; Digital IC; Testing; RHBD
• Online Access: https://hdl.handle.net/10356/177249
• Institution: Nanyang Technological University

Digital electronics in space and high-level autonomous vehicles are required to feature an ultra-low soft error rate (SER ≤ 10FITS) – an SER unattainable by consumer-grade digital electronics. This project is part of a joint project between NTU, Zero-Error Systems Pte Ltd (ZES) and the Institute of Microelectronics (IME), A*STAR to design an ultra-low-SER RISC-V microprocessor. The approach is based on the Radiation-Hardened-By-Design (RHBD) techniques, involving a new RHBD cell library. The RHBD cell library requires verification of its cells in terms of SER under irradiation. For verification, test structures need to be designed to detect the soft errors, thereby ascertaining the radiation hardness of the cells. However, when characterizing a large quantity of cells, reported test structures induce an exorbitant cost, owing to either the large test die area overhead or the unacceptably long test hours. This research-based Final Year Project (FYP) pertains to the said test structures, with the objectives of addressing the aforesaid challenges. Specifically, this FYP proposes a novel test structure design involving our proposed Multi-Error-Lock-Trace (MELT) mechanism. This proposed mechanism serves to temporarily lock the soft error into registers, and thereafter trace back to the location of the error occurrence. We implement four test structures based on our aforementioned proposed MELT strategy. The proposed methodology is very worthwhile. Specifically, when compared to the reported approach of assigning individual I/O pads for each device-under-test (DUT), our method reduces the number of I/O pads by 89%, translating to >95% die area reduction. Further, when compared to the other reported approach of multiplexing I/O pads for each DUT, our method reduces the number of test hours by >80%. In this FYP, we further realized the proposed microprocessor in an FPGA to verify its software design and to benchmark its core performance. This FYP has met all stipulated objectives and the outcomes, including a paper to be presented at the IEEE Custom IC Conference 2024, a paper to be presented at the IEEE Midwest Symposium on CAS 2024, and an impending technical disclosure of a patent.