Channel modeling and FPGA implementation for magnetic recording
This report aims to design and implement a channel model on the Xllinx Spartan-3E XC3S500E Field Programmable Gate Array (FPGA) board. The channel model basically comprises of two main parts, a Finite Impulse Response (FIR) filter and an irregular Low- Density Parity-Check (LDPC) encoder.
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| Format: | Final Year Project |
| Language: | English |
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2009
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| Online Access: | http://hdl.handle.net/10356/17851 |
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| Institution: | Nanyang Technological University |
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sg-ntu-dr.10356-178512023-07-07T16:12:09Z Channel modeling and FPGA implementation for magnetic recording Tan, Jing Jie. Goh Wang Ling School of Electrical and Electronic Engineering Centre for Integrated Circuits and Systems DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits This report aims to design and implement a channel model on the Xllinx Spartan-3E XC3S500E Field Programmable Gate Array (FPGA) board. The channel model basically comprises of two main parts, a Finite Impulse Response (FIR) filter and an irregular Low- Density Parity-Check (LDPC) encoder. Bachelor of Engineering 2009-06-17T03:44:45Z 2009-06-17T03:44:45Z 2009 2009 Final Year Project (FYP) http://hdl.handle.net/10356/17851 en Nanyang Technological University 131 p. application/pdf |
| institution |
Nanyang Technological University |
| building |
NTU Library |
| continent |
Asia |
| country |
Singapore Singapore |
| content_provider |
NTU Library |
| collection |
DR-NTU |
| language |
English |
| topic |
DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits |
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DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits Tan, Jing Jie. Channel modeling and FPGA implementation for magnetic recording |
| description |
This report aims to design and implement a channel model on the Xllinx Spartan-3E
XC3S500E Field Programmable Gate Array (FPGA) board. The channel model basically
comprises of two main parts, a Finite Impulse Response (FIR) filter and an irregular Low-
Density Parity-Check (LDPC) encoder. |
| author2 |
Goh Wang Ling |
| author_facet |
Goh Wang Ling Tan, Jing Jie. |
| format |
Final Year Project |
| author |
Tan, Jing Jie. |
| author_sort |
Tan, Jing Jie. |
| title |
Channel modeling and FPGA implementation for magnetic recording |
| title_short |
Channel modeling and FPGA implementation for magnetic recording |
| title_full |
Channel modeling and FPGA implementation for magnetic recording |
| title_fullStr |
Channel modeling and FPGA implementation for magnetic recording |
| title_full_unstemmed |
Channel modeling and FPGA implementation for magnetic recording |
| title_sort |
channel modeling and fpga implementation for magnetic recording |
| publishDate |
2009 |
| url |
http://hdl.handle.net/10356/17851 |
| _version_ |
1772825886375018496 |