Design, fabrication and characterization of a tunnel FET
This report details and demonstrates a vertical silicon nanowire (SiNW) based tunneling field-effect transistor (TFET) using CMOS compatible technology. With Si P+-i-n+ tunneling junction, the TFET with a gate length of ~200 nm exhibits good subthreshold swing of ~70 mV/dec, superior DIBL of ~17 mV/...
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2009
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| Online Access: | http://hdl.handle.net/10356/17918 |
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sg-ntu-dr.10356-179182023-07-07T17:44:46Z Design, fabrication and characterization of a tunnel FET Chen, Zhixian. Yu Hongyu School of Electrical and Electronic Engineering A*STAR Institute of Microelectronics DRNTU::Engineering::Electrical and electronic engineering::Nanoelectronics This report details and demonstrates a vertical silicon nanowire (SiNW) based tunneling field-effect transistor (TFET) using CMOS compatible technology. With Si P+-i-n+ tunneling junction, the TFET with a gate length of ~200 nm exhibits good subthreshold swing of ~70 mV/dec, superior DIBL of ~17 mV/V, and excellent Ion/Ioff ratio of 7 orders with a low Ioff (~7pA/um). The vertical SiNW based TFET is proposed to be an excellent candidate for ultra-low power and high density applications. Bachelor of Engineering 2009-06-18T01:21:14Z 2009-06-18T01:21:14Z 2009 2009 Final Year Project (FYP) http://hdl.handle.net/10356/17918 en Nanyang Technological University 60 p. application/pdf |
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Singapore Singapore |
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DRNTU::Engineering::Electrical and electronic engineering::Nanoelectronics |
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DRNTU::Engineering::Electrical and electronic engineering::Nanoelectronics Chen, Zhixian. Design, fabrication and characterization of a tunnel FET |
| description |
This report details and demonstrates a vertical silicon nanowire (SiNW) based tunneling field-effect transistor (TFET) using CMOS compatible technology. With Si P+-i-n+ tunneling junction, the TFET with a gate length of ~200 nm exhibits good subthreshold swing of ~70 mV/dec, superior DIBL of ~17 mV/V, and excellent Ion/Ioff ratio of 7 orders with a low Ioff (~7pA/um). The vertical SiNW based TFET is proposed to be an excellent candidate for ultra-low power and high density applications. |
| author2 |
Yu Hongyu |
| author_facet |
Yu Hongyu Chen, Zhixian. |
| format |
Final Year Project |
| author |
Chen, Zhixian. |
| author_sort |
Chen, Zhixian. |
| title |
Design, fabrication and characterization of a tunnel FET |
| title_short |
Design, fabrication and characterization of a tunnel FET |
| title_full |
Design, fabrication and characterization of a tunnel FET |
| title_fullStr |
Design, fabrication and characterization of a tunnel FET |
| title_full_unstemmed |
Design, fabrication and characterization of a tunnel FET |
| title_sort |
design, fabrication and characterization of a tunnel fet |
| publishDate |
2009 |
| url |
http://hdl.handle.net/10356/17918 |
| _version_ |
1772829086135091200 |