Design, fabrication and characterization of a tunnel FET

This report details and demonstrates a vertical silicon nanowire (SiNW) based tunneling field-effect transistor (TFET) using CMOS compatible technology. With Si P+-i-n+ tunneling junction, the TFET with a gate length of ~200 nm exhibits good subthreshold swing of ~70 mV/dec, superior DIBL of ~17 mV/...

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Bibliographic Details
Main Author: Chen, Zhixian.
Other Authors: Yu Hongyu
Format: Final Year Project
Language:English
Published: 2009
Subjects:
Online Access:http://hdl.handle.net/10356/17918
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Institution: Nanyang Technological University
Language: English

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