Hardware accelerator for feature matching with binary search tree

Hardware accelerator for feature matching with binary search tree

Feature matching is an essential step for autonomous robot to localize itself during navigation. However, it is often difficult to achieve the matching in real-time due to limited on-board computing resources. We present an FPGA implementation for stream-processing based feature matching called Bina...

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書目詳細資料
Main Authors:	Thathsara, Miyuru, Lam, Siew-Kei, Kawshan, Damith, Piyasena, Duvindu
其他作者:	College of Computing and Data Science
格式:	Conference or Workshop Item
語言:	English
出版:	2024
主題:	Computer and Information Science Feature matching FPGA Binary search tree Hardware acceleration
在線閱讀:	https://hdl.handle.net/10356/179622
標簽:	添加標簽沒有標簽, 成為第一個標記此記錄!

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