FPGA development for HDD servo demodulation
This final year project involves the development for Hard Disk Drive (HDD) servo demodulation. To achieve this, algorithms of timing recovery in digital data have been introduced and a Digital Phase-Locked Loop (DPLL) has been designed by using ALTERA®’s industrial design software Quartus® II. The D...
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| Format: | Final Year Project |
| Language: | English |
| Published: |
2009
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| Online Access: | http://hdl.handle.net/10356/18058 |
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| Institution: | Nanyang Technological University |
| Language: | English |