FPGA development for HDD servo demodulation

• Main Author: Shi, Yi Jun.
• Other Authors: Xue Ping
• Format: Final Year Project
• Language: English
• Published: 2009
• Subjects: DRNTU::Engineering
• Online Access: http://hdl.handle.net/10356/18058
• Institution: Nanyang Technological University

This final year project involves the development for Hard Disk Drive (HDD) servo demodulation. To achieve this, algorithms of timing recovery in digital data have been introduced and a Digital Phase-Locked Loop (DPLL) has been designed by using ALTERA®’s industrial design software Quartus® II. The DPLL is then going to be implemented to the ALTERA®’s Stratix II 90-nm FPGA. In the first part of this report, the background knowledge about HDD servo and DPLL will be introduced. Further, the algorithms, which are developed to obtain the servo information such as phase from the signal of servo pattern, will be discussed. By these algorithms the phase difference can be detected and will be used to verify the effect of DPLL. In the second part of the report, the design of DPLL will be discussed. With the help of Quartus® II, it is convenient to design a DPLL in the block diagram, as well as to perform the test and simulation works on computers. Examples will be shown during the report. Further, the DPLL block diagrams can be converted into programming code, which is to be burned into FPGAs for use. Conclusions and further works will be discussed at last part of the report.