Design and implementation of a non-iterative division circuit

• 主要作者: Zhang, Dawei
• 其他作者: Jong Ching Chuen
• 格式: Thesis-Master by Coursework
• 語言: English
• 出版: Nanyang Technological University 2024
• 主題: Engineering
• 在線閱讀: https://hdl.handle.net/10356/181331
• 機構: Nanyang Technological University

Arithmetic division is frequently used in digital signal processing, and very often in image and video processing, where high computational performance is required but a small deviation from the accurate value is allowed. In this dissertation, a digital divider circuit is proposed to carry out non-iterative arithmetic division between two 22-bit binary floating points. In this non-iterative division, the quotient forms a curved surface, which can be partitioned into several strips. To simplify the computation, and hence hardware complexity, each strip of the curved surface is then represented by a flat plane. Linear programming is used to find the flat plane with best fit to the curved surface, i.e., minimum difference between the curved surface and the fitted plane (minimum error). With different number of partitions, the resultant minimum errors in terms of the Maximum Absolute Error Percentage (MAEP) range from 0.13% to 1.27%. A digital circuit is then designed to perform the division based on the proposed method. This digital circuit is coded in Verilog HDL. It is also simulated and synthesized on both FPGA and TSMC 45nm/65nm CMOS technology, to illustrate its adaption to different implementation platforms and processes. Compared with a Xilinx IP Divider, the proposed divider could achieve 88.9% LUT saving and 45% power reduction. Compared to the divider implementation using STM 90nm CMOS, the proposed divider implemented on a low power 65nm and 45nm CMOS achieved up to 67.7% reduced latency and up to 72.8% area savings. This dissertation documents the formation of the algorithm, the linear programming used to obtain the fitted planes, the design and implementation of the digital circuits, and the results.